(a) Field of the Invention
The present invention relates to a chip testing circuit, and more particularly, to a chip testing circuit that increases the testing throughput.
(b) Description of the Related Art
Because of the small size and the powerful functionalities of an integrated circuit (IC), the integrated circuit has become one of the indispensable electronic components of the information technology related equipments. In order to make sure that the chips are working normally, all the chips must go through rigorous testing before shipped out of the factory. For example, a simple testing method inputs a known test signal into the circuit of the chip and then retrieves the cell signal from the circuit of the chip to determine whether the function of the chip is normal or not.
FIG. 1A shows a schematic diagram illustrating the write portion of a chip testing circuit 100 in the prior art. The write portion of the chip testing circuit 100 is coupled to the chip testing system (such as a probe card) via the first interface circuit 11 to receive the test signal TS outputted by the chip testing system and to transmit the test signal TS to the write unit 12. The write unit 12 is coupled to a DRAM cell array 1001 of the chip for inputting the test signal TS to the DRAM cell array 1001 of the chip. In order to increase testing efficiency, the first interface circuit 11 is coupled to a plurality of write units 12 so that the first interface circuit 11 can simultaneously input the testing signal TS into the write units 12 of the same write group 12a. 
FIG. 1B shows a schematic diagram illustrating the read portion of a chip testing circuit 100 in the prior art. The read unit 22 receives the cell signal FS transmitted from the DRAM cell array 1001 of the chip and transmits the cell signal to the second interface circuit 21. On the other hand, the read units 22 of the same read compressing group 22a transmit the cell signal FS to the compressing circuit 23 for compression in order to generate a compressing signal CS. The compressing signal CS is then transmitted to the second interface circuit 21. The second interface circuit 21 then generates a determining signal DS according to the statuses of a cell signal FS and the compressing signal CS and transmits the determining signal to the chip testing system. Thus, the chip testing system can confirm whether the DRAM cell array 1001 of the chip is normal or not according to the determining signal DS.
As shown in FIG. 1B, each second interface circuit 21 can access the testing results of the four circuits of the chip that are coupled to the read units 22. This is the traditional four-terminal input/output signal compressing method (IO compress4 method) commonly used in the industry. However, according to the above-mentioned traditional architecture of the chip testing circuit, two dedicated pins must be utilized to couple the two first interface circuits 11 and the two second interface circuits 21 to the two probes of the chip testing system for correctly testing the chip. Therefore, the number of pins for testing will be increased and the testing cost for the chip will be increased as well. In order to increase the testing speed, more probes have to be used and the overall production cost is further increased.